This application relates to ferroelectric thin films which are used in nonvolatile memories and specifically to a C-axis oriented ferroelectric used in a metal-ferroelectric-metal-silicon semi-conductor. Known ferroelectric random access memories (FRAM) are constructed with one transistor (1T) and one capacitor (1C). The capacitor is generally made by sandwiching a thin ferroelectric film between two conductive electrodes, which electrodes are usually made of platinum. The circuit configuration and the read/write sequence of this type of memory are similar to that of conventional dynamic random access memories (DRAM), except that no data refreshing is necessary in a FRAM. Known FRAM devices, however, have a fatigue problem that has been observed in the ferroelectric capacitor, which is one of the major obstacles that limits the viable commercial use of such memories. The fatigue is the result of a decrease in the switchable polarization (stored nonvolatile charge) that occurs with an increased number of switching cycles. As used in this case, "switching cycles" refers to the sum of reading and writing pulses in the memory.
Another known use of ferroelectric thin films in memory applications is to form a ferroelectric-gate-controlled field effect transistor (FET) by depositing the ferroelectric thin film directly onto the gate area of the FET. Such ferroelectric-gate controlled devices have been known for some time and include devices known as metal-ferroelectric-silicon (MFS) FETs. FRAMs incorporating the MFS FET structure have two major advantages over the transistor-capacitor configuration: (1) The MFS FET occupies less surface area, and (2) provides a non-destructive readout (NDR). The latter feature enables a MFS FET device to be read thousands of times without switching the ferroelectric polarization. Fatigue, therefore, is not a significant concern when using MFS FET devices. Various forms of MFS FET structures may be constructed, such as metal ferroelectric insulators silicon (MFIS) FET, metal ferroelectric metal silicon (MFMS) FET, and metal ferroelectric metal oxide silicon (MFMOS) FET.
There are a number of problems that must be overcome in order to fabricate an efficient MFS FET device. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on silicon. Such structure is shown in U.S. Pat. No. 3,832,700. Additionally, it is very difficult to have a clean interface between the ferroelectric material and the silicon. Further, there is a problem retaining an adequate charge in the ferroelectric material. A ferroelectric memory (FEM) structure on a gate region is shown in U.S. Pat. No. 5,303,182, which emphasizes that the transfer of metal ions into the gate region is undesirable. Similar structure is shown in U.S. Pat. No. 5,416,735.
Film deposition techniques may be broadly classified as physical vapor deposition (PVD) and chemical processes. The chemical processes may further be broken down into chemical vapor deposition (CVD) and wet chemical processes, including sol-gel and metalorganic decomposition (MOD).
Physical vapor deposition (PVD), has the advantages of (1) dry processing, (2) high purity and cleanliness, and (3) compatibility with semiconductor integrated circuit processing. PVD results in a Pb.sub.5 Ge.sub.3 O.sub.11 layer that (1) has low throughput, (2) has poor step coverage, and (3) may require high-temperature, post-deposition annealing, and which, in the case of complicated compounds, suffers from difficult stoichiometric control. PVD techniques include electron-beam evaporation, RF diode sputtering, RF magnetron sputtering, DC magnetron sputtering, ion beam sputtering, molecular beam epitaxy and laser ablation.
Sol-gel and MOD processes may be used, as these are simple processes, that provide molecular homogeneity, good composition control and low capital costs. However, these processes frequently result in film cracking when used for FE thin film formation because of large volume shrinkage during post deposition annealing.